The present invention relates generally to serial data communication and transmission applications in the manufacture of integrated circuits needed as physical interface to any type of serial bus (in this example USB). More particularly, the present invention relates to clock and data recovery logic for a serial data stream, which supplies a sync lock within 1.5 bit times, insuring clock and data information is recovered in these applications. The CDR function is implemented as a plesiochronous technique with no feedback to a PLL. It also has no lock detection, nor loss of lock detection, nor loss of sync detection. In the intended application, those functions are integrated into the logic coupled to the recovered CLK and DATA.
With the recent increased speed of computers and the need for high performance peripherals, the use of high speed serial data communications applications in integrated circuits built to physically interface to any given bus has increased correspondingly.
USB (Universal Serial Bus) 1.1, has been the de facto external connectivity standard between computers and their peripherals in serial communications up to 12 Mbps (Million bits per second). As the need for faster communications and higher performance peripherals has grown, computer and peripheral manufacturers have responded with a new higher speed standard: USB 2.0.
USB 2.0 increases the device data throughput up to 480 Mbps, 40 times faster than USB 1.1 devices while maintaining or improving on other USB 1.1 specifications such as the Microsoft Plug and Play feature, and numerous other technical specifications, some of which will be discussed in relation to the present invention. USB 2.0 even challenges FireWire (IEEE 1394) currently at 400 Mbps, as the serial interface of the future. Three speed modes are available under the new USB 2.0 standard: high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps).
Conventionally, an incoming serial data stream may be NRZI (Non-Return-to-Zero Inverted) encoded and bit stuffed. NRZI is a data transmission method in which the polarity of the bit is reversed whenever a 0 bit is encountered, and a static voltage level is transmitted whenever a 1 bit is encountered as illustrated in FIG. 1, and designated at reference numeral 110. NRZI thus uses the presence or absence of a transition to signify a bit (indicating a logical 0 by inverting the state). Combined with bit-stuffing, where an extra 0 bit is inserted after every six consecutive 1 bits, this data encoding causes a guaranteed transition every 7 bit times when a data payload would be all 1 bits. Every transition gives the CDR circuit phase information that it uses to align it""s recovered clock to the phase of the incoming data. The less time between transitions, the less phase error which is to be expected caused by frequency offset. Other techniques used are, for example, 8b-10b coding similar to 1394 and Ethernet.
The structure of the data stream follows a specific communications protocol, which defines the rules for sending a block of data (each known as a Protocol Data Unit (PDU)) (e.g., 150 of FIG. 2) from one node in a network to another node. The exchanged PDUs comprises three parts: a sync sequence 160, a packet payload (also known as a Service Data Unit (SDU)) 170, and an End of Packet (EOP) 180. The protocol does not define or constrain the data carried in the payload portion 170 of the data block. The protocol does, however, specify the format of the sync sequence.
Packet switching refers to protocols in which a longer message (the data) exceeding a network-defined maximum length is divided into short message packets before they are transmitted. Each packet, with an associated header with information for routing the packet from origination to destination, is then transmitted individually and can even follow different routes to its destination. Once all the packets forming a message arrive at the destination, they are recompiled into the original message. Most modern Wide Area Network (WAN) protocols, including the successful TCP/IP protocol, as well as X.25, and Frame Relay, are based on packet-switching technologies.
A fundamental difference between packet communication and conventional, continuous-type communication is that the data is formed into packets as described above. When there is no data to be sent, the bus is put into an ideal state that shows no change in voltage levels. Continuous-type protocols is would fill the idle time within a frame with well-known xe2x80x9cidlexe2x80x9d patterns which are used to occupy the link when there is no data to be communicated. A packet network equipment discards the xe2x80x9cidlexe2x80x9d patterns between packets and processes the entire packet as one piece of data. The equipment examines the packet header information (PCI) and then either removes the header (in an end system) or forwards the packet to another system. If the out-going link is not available, then the packet is placed in a queue until the link becomes free. A packet network is formed by links which connect packet network equipment.
In the packet switching used in USB 2.0 at 480 Mbps, one portion of the packet header 160 will contain at least 12 sync bits indicated by an alternating pattern, intended to allow the sending and receiving clocks time to synchronize. The packet payload 170 will contain up to 1024 bits, while the end-of-packet 180 contains 8 bits.
The incoming data stream is assumed to be sent with a clock of the same frequency as the local clock used in the receiving system, but shows all jitter components of an electrical transmission over a bandwidth limited media (e.g., data dependant cycle to cycle jitter).
A conventional linear clock and data recovery (CDR) circuit attempts to recover the original transmitting clock by utilizing a phase detector (PD) or alternatively a phase-frequency detector (PFD), and source a charge pump followed by a VCO of an analog PLL. The resulting change in phase and frequency is sourced back to the PD/PFD to be compared to the next data. These conventional linear techniques use an analog PLL, which need an undefined number of transitions, are dependant on the PLLs bandwidth, the data-rate to VCO frequency ratio and more. In addition, data derived by these conventional linear techniques cannot be guaranteed by the USB synch packet (typically Nxc3x9710e3 needed vs 6 available in USB FS mode).
The capture range of a PLL is typically narrow, and usually requires the help of a frequency acquisition aid and special training sequences which have the disadvantage of limited availability.
Other conventional plesiochronous techniques to minimize the effect of metastable readings give unreliable phase information. To do so, most of these techniques try to average the results before selecting a new phase. This also requires a continuous bitstream that is not available in USB applications.
The analog types require many special analog components, including rectifier component(s), differentiator component(s), etc. These components are difficult to implement in ASIC devices, and when not carefully designed may not function properly under all conditions. The digital implementations have at most +/xe2x88x9250% usable frequency range, but are often narrower depending on the implementation and the statistics of the input data.
For a number of reasons such as bus turn around timing (the time measured at the USB host controller, from the sending of a request to the farthest bus subscriber, until receipt of an acknowledge package), a USB HUB is allowed to strip-off a defined number of sync bits during the HS repeater mode which results in a minimum sync pattern of 12 alternating bits at the receiver of a subscriber. Under FS conditions the sync field consists of 6 bits from the start. This is not enough sync bits for conventional CDR techniques.
Another prior art CDR methodology is illustrated in FIG. 3 and designated at reference numeral 200. The CDR 200 uses a crystal oscillator 220 to drive a PLL along with frequency dividers 230 to produce two phases of a local clock (CLK, and CLK(NOT)) 235 which enter the CDR circuit 210. The serial data stream is decoded from a USB transmitter/receiver 240 to a single ended signal DATA 245 which also enters the CDR circuit 210. Two 4-bit shift registers 260, 270 are incorporated to store 8 bits of the serial data. A voting logic circuit 290 is employed to select one of the clock phases, while averaging sample points 280, 285 of the 8 data bits to minimize the effects of metastable conditions in the CDR circuit 210. The selected phase 291 from the voting logic 290 then provides feedback 291 to control the PLL clock frequency 230 and is then used by gate logic 295, to gate the data stream to recover the clock and the data 297. The disadvantage of this scheme is that there is an 8 bit time-delay while the bits fill both shift registers before the clock frequency and phase can be established. In addition, and as described above, after a number of rerouting operations there may not be enough sync bits remaining to provide lock and may cause a loss of data. Here again, jitter in the data stream or isolated bit errors may also cause the PLL to lose lock, as the PLL frequency and lock is dependant on the feedback loop from the voting logic 290.
Accordingly, considering the substantially higher data rates used in the new USB 2.0 at 480 Mbps, the new 350 ps cycle to cycle jitter specification under HS conditions (1 bit=2.08 ns ), and the increased use of hubs and routers, there is a need for a CDR circuit which is able to quickly lock to a serial data stream, have a high jitter tolerance, and yet eliminate the effects of metastable conditions inherent in CDR circuits used in high speed serial data communications applications of ASIC and microprocessor chips.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Its primary purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The invention is directed to a quick locking (e.g., within two sync bit times) clock and data recovery (CDR) circuit used in high speed data communications applications (e.g., ASIC and microprocessor chips). The CDR circuit takes multiple (e.g., 8) phases of the local clock, which are offset (e.g., by 45 degrees), and uses the multiple phases to latch the state of data at multiple times, and uses the latched data to determine which of the multiple phases captured a data transition. The CDR circuit compares the indicated phase to the phase used to capture a previous data transition and uses such information to, produce a stable selection of a clock phase. The selected clock phase is then employed to provide a recovered clock and data signal in association with the incoming serial data stream independent of jitter and free of metastable conditions.
In accordance with the present invention, a CDR circuit for a serial data stream is disclosed. The CDR circuit requires only one data transition on the incoming data stream in order to pick one of the 8 clock phases for accurate data recovery. In one exemplary aspect of the invention, for every transition, there is a decision made as to the phase to be selected, in order to enable subsequent related logic to securely latch the data to produce a recovered clock and data signal. Thus, a feature of the present invention is that nearly xe2x80x9cinstant lockxe2x80x9d is provided, as only the first bit of the incoming data stream is lost to achieve pattern lock, while other designs need much more pattern or bits to lock.
The CDR circuit of this invention, therefore, provides recovered clock and data signals with a quasi-fixed phase relationship even though the serial data jitters. Also, as there is no feedback to the VCO or a PLL, the CDR system of the present invention avoids the usual PLL feedback loop problems previously discussed.
The present invention utilizes a plurality of input phases (e.g., 8) of the local clock running at approximately the same nominal frequency of the transmitting clock. The phase offset between successive phases when the number of phases is eight is about 45 degrees. Therefore, the CDR circuit of the current invention may be used in any application where multiple phases offset from one another (e.g., about 45 degrees) of the receiving/sending clock are available (e.g., from a local VCO).
The CDR circuit of the present invention also provides about 2 phase differences (e.g., about 2xc3x97260 ps=520 ps) of cycle to cycle jitter tolerance at 480 MHz, which is substantially greater than the 350 ps cycle to cycle jitter tolerance required by USB 2.0, and permits standard ASIC FFs (Flip-Flops) to be used. According to one exemplary aspect of the invention, the incoming data stream may experience frequency wander far greater than specified without causing loss of lock or loss of data. Thus no loss of lock or loss of data circuitry is required. However, if two different frequencies are used in such an exemplary case, a periodic phase shift on the recovered CLOCK_OUT will result. This, in principal, would add to the jitter transfer function of a CDR circuit. However, in any application that provides a deserializer function (serial to parallel conversion), this figure of merit is irrelevant as the deserializer can handle those events using FIFOs.
An advantage of the present invention is that the CDR does not average sample points of the data as most other CDR circuits do. Averaging in CDR circuits is done to avoid the effect of metastable conditions which cannot be avoided in CDRs. The CDR described in accordance with the present invention has an alternative way to handle and eliminate the metastable conditions which avoids averaging and allows fast locking.
Another advantage of the present invention, is that the CDR integrated circuit implementation may be small (e.g., about 300 gates).
Still another advantage of the present invention, is that the CDR solution works well at low and high frequencies of over 480 MHz (multifrequency CDR).
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.